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TEST STANDARDS AND METHODS Electrostatic Discharge (ESD) Dilemma Electrostatic Discharge (ESD): A Defintion Links to Standards and Reference Sites Electrostatic Discharge (ESD) Dilemma It is a continuing trend. Electronic equipment manufacturers and users continue to demand faster, increasingly complex devices in smaller packages at lower costs. Device manufacturers meet those demands by shrinking geometries and increasing functionality on chip real estate. As these devices grow more crowded and clearances and line thicknesses approach theoretical limits, devices are becoming increasingly susceptible to damage by electrostatic discharge (ESD). ESD's short, fast, high-amplitude pulses are an inevitable part of the day-to-day environment of both chips and equipment. In fact, ESD is the leading cause of device failure in the field. Device immunity to ESD is therefore a major consideration in the design, application and purchase of electronic components. To be dealt with adequately, it must be characterized. Characterization allows device users to make appropriate compromises between ESD protection costs, product reliability and product performance. The only method that provides confidence as to a device's ESD immunity level is by testing that device. But qualifying device's has been a challenge because of the difficulty applying repeatable, nanosecond rise time waves to any selected device pin. To compound the test problem, device pin counts have increased and qualifying tests have thus become more time consuming requiring from hours to days to test one device. With the range of devices on the market, various ESD test systems are required. KeyTek's range of component reliability products meet the different testing challenges faced by semiconductor manufacturers in a reliable and cost-effective manner.
Electrostatic Discharge (ESD): A Definition Electrostatic Discharge (ESD): A current flow between two objects with different electrostatic potentials. This definition, although accurate, requires a little further qualification to be relevant in terms of device testing. Specifically, it should be remembered that with device ESD, we are normally concerned with rapid current flows. The destructive mechanism associated with ESD in devices is primarily melting of the device material due to high temperatures. Although sometimes with very rapid events, the damaged mechanism can be punched through the oxide layer due to high electrical field strengths. Devices will normally experience an ESD event during normal handling and operating conditions. A typical and often used example is that of an operator gathering charge by walking across a carpet and then handling a device. As the operator touches the device (at high voltages a discharge can occur before physical contact), there is a rapid equalization of potentials between the operator and device. While very unlikely to happen in this way today with modern manufacturing environments and procedures, the example is still one many of us have experienced. Destructive discharges can be undetectable by a human operator since the energy levels involved are often very small and below human thresholds for detection. However, for a device these discharges can be and often are fatal. Although the energy may be low, the device must dissipate it as heat. Silicon is a very poor conductor and therefore small levels of energy delivered quickly can easily cause the material to melt and deform due to the silicon's inability to dissipate the heat fast enough. After the material has been deformed by the high localized temperature, the device is permanently damaged. It is important to remember that not all ESD discharges are instantly fatal, many will only weaken the device making it less likely to provide reliable and long-term operation. Due to the nature of ESD, it must be assumed that all devices will encounter an event during the normal course of their lifetime. Hence, ensuring that devices provide a reasonable and acceptable level of tolerance to ESD is an important part of all device design and manufacturing programs. To determine the ESD threshold of a device, it is necessary to agree on the type of ESD stress for which testing will take place. There are presently three major ESD stress types:
Within each of these basic categories are a number of applicable standards. To learn more about the aforementioned standards, please visit the appropriate web pages of the organizations and committees responsible for the management and release of various industry standards. Latch-up is the term traditionally used to describe the condition that exists within a CMOS device after its internal parasitic SCR (Silicon Controlled Rectifier) has been triggered into conduction. An SCR is a device that is available as a stand-alone discrete component from a number of semiconductor manufacturers. It is a three-terminal component. The three terminals comprise a Cathode, Anode and Gate. The Gate input is used to inject a small current that, when greater than a defined trigger value, will cause the device to conduct current between the Cathode and Anode. Once in a conducting state, the SCR cannot be turned off until the current flow through it falls below a specified minimum value. It is a very useful and widely used component in its discrete form. The very features that make it a powerful and flexible component in a discrete form, are the same features that make it a very undesirable component when incorporated within an integrated circuit. In a CMOS structure, a SCR is inherently constructed between the supply rails of the device, thus when triggered into conduction, the SCR shorts out the supply causing a high current to flow. This high current typically destroys the device and can often cause the entire system in which the device is operating to fail. Since the SCR is inherent, its affect and the likelihood of it being triggered must be minimized. There are various techniques the device manufacturer can use to accomplish this, however, this does not remove the need to test the device and ensure that new and old devices continue to meet acceptable threshold levels. Triggering of an SCR can occur under a number of conditions. The more common of these are generally:
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