Our manufacturing services can handle the entire PFC wafer bumping and assembly Process, or any combination of individual steps:

Wafer metallization and redistribution	An electroless plating technique uses zinc and palladium to ensure bond pads will achieve lower contact resistance than gold. If necessary, bond pads can be redistributed from the periphery to the center of the chip.
Wafer Bumping	High-resolution stencil printers to create a dense peripheral or array pattern of conductive polymer bumps.
Dicing wafers into chips	Bumped wafers are diced into chips, which are then waffle packed prior to assembly.
Known good die testing	We offer low-cost known good die testing and burn-in.
Chip-to-substrate assembly	Using fully automatic flip chip aligner-bonders, the chip is assembled to the substrate.
Electrical testing	We provide final testing to your specification.
Our technology services range from helping you consider PFC scenarios to helping you create your own PFC production facilities:
Application evaluation	Our development laboratory can evaluate and optimize solutions for potential PFC applications.
Interconnect design	We can assist your chip designers in creating an ideal bond pad layout for implementing a flip chip PFC interconnect pattern.
Prototyping	We will conduct small product runs to optimize your implementation of the PFC process.
Licensing	We make our PFC expertise and patents available through expedited, user-friendly licensing options.
Training	Complete technology-transfer training is available for PFC licensees.
Technical support	Our engineering staff is ready to assist you with all aspects of PFC processing.